For decades, semiconductor manufacturers have been shrinking transistor size in ICs to achieve the yearly increases in speed and performance described by Moore's Law—chip performance will double every ˜18 months. Moore's Law exists only because the RC delay has been negligible in comparison with signal propagation delay. For submicron technology, however, RC delay becomes a dominant factor. It was hoped that change to copper metallurgy, low-k dielectrics and chemical mechanical polishing (CMP) would lower the RC delay and allow the performance increases predicted by device scaling and Moore's Law to continue through this decade.
While copper and CMP have been integrated smoothly into the IC fabrication process, the same cannot be said for spin-on or CVD low-k dielectrics. To lower the permittivity and thus the line capacitance, IC manufacturers were forced to resort to materials with no prior history in chip production. The semiconductor industry has postponed three times (three nodes) the transition to true low-k (k<2.8) ILDs, with reliability and yield problems being the major suspects for the implementation delays.
This inability to smoothly integrate low-k has generated many discussions concerning the end of device scaling as we know it, and has hastened the search for solutions beyond the perceived limits of current 2-D silicon devices. One emerging solution is 3-D integration also referred to as 3D interconnect. 3D interconnect structures are advantageously not only because of the size reduction, other drivers are mainly the fact that in 2D structures long interconnects are too slow and consume too much power. If a large number of these long interconnects needed in 2-D structures could be replaced by short vertical interconnects, this would greatly enhance performance. While silicon real estate is consumed by the vertical interconnect, a significant inter-wafer interconnect density can be achieved with a minimal area penalty. FIG. 1 illustrates a 2D- versus 3-D integration scheme and clearly shows that a large number of the long. interconnects needed in 2-D structures could be replaced by short vertical interconnects and greatly enhance performance. In particular, stacking just two wafers should offer an increase in performance by 15%, decrease power by 30% and reduce cost by 15% simply due to the decreased path lengths and required layers of metal to connect the transistors.
In prior art several solutions are described to realize a 3D stacking of wafers in which the direct wafer to wafer (or die to die) stacking with vertical connections through the silicon are realized by means of “through wafer” vias filled with copper. These through wafer vias are etched after completion of the full Front End of Line (FEOL) processing and often after complete BEOL processing. A modified damascene technique is used to fill said through wafer vias with conductive material such as copper.
In the realization of these “through wafer” vias or deep vias there are still a lot of problems to be solved. A first problem is related to the thermal budget available after etching the deep via through the BEOL, FEOL and subsequent silicon substrate. These deep vias are filled with conductive materials such as copper, a barrier layer such as TaN and optionally a copper seed layer. To isolate said conductive materials from the bulk of the substrate there is a need to deposit a dielectric isolator (liner) within the via. Typically, these dielectric isolators (e.g. TEOS oxide) are deposited before the deposition of said conductive materials by means of thermal and plasma enhanced deposition techniques (such as LP-CVD, ALD, PE-CVD, . . . ) which typically have a rather high thermal budget which is not compatible at that stage of the processing (thermal budget is preferably lower than 450° C.).
A second problem to the creation of said deep vias is related to hardmask selective (etch) processing, which is very difficult to achieve at that stage of the processing. A very thick hardmask layer needs to be deposited (to avoid damage to layers underneath) which leads to hardmask residues afterwards that need to be removed by e.g. Chemical Mechanical Polishing (CMP). Said CMP processing is very critical and difficult to perform at that stage of the processing, e.g. damage to the W contact plugs is absolutely to be avoided.
In U.S. Pat. No. 6,448,174 via holes are created after full completion of FEOL and BEOL processing. These vias are first filled with an organic adhesive layer such that a handling wafer (also called carrier wafer) could be glued onto the top substrate. Subsequently the backside of the wafer is thinned as far as the via holes such that these vias are opened from the back and connected in subsequent processing to a second wafer surface. The carrier wafer and organic adhesive are then removed and the via is filled with conductive material such as tungsten.
In U.S. Pat. No. 6,645,832 first two wafers containing active IC devices (after finishing a full FEOL and BEOL processing) are bonded together via a metal bonding layer deposited on opposing (top) surfaces of both wafers at designated bonding areas such that electrical connections between active devices on both wafers are established. After the wafer bonding is completed one or more interwafer vias are etched in the top wafer top establish electrical connections of the active devices of both wafers and an external interconnect